再構成可能コンピューティング
出典: フリー百科事典『ウィキペディア(Wikipedia)』 (2023/12/14 17:43 UTC 版)
関連項目
- プログラマブルロジックデバイス (PLD) - FPGA は PLD の一種。
- ハードウェア記述言語 (HDL)
- 動的再構成
- 1チップMSX
外部リンク
- The Fine-grained Computing Group at Information Sciences Institute 南カリフォルニア大学
- Reconfigurable computing lectures and tutorials at Brown University
- The University of South Carolina Reconfigurable Computing Laboratory
- The Virginia Tech Configurable Computing Laboratory
- Reconfigurable Systems Summer Institute (RSSI)
- IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
- International Conference on Field-Programmable Logic and Applications (FPL)
- NSF Center for High-Performance Reconfigurable Computing (CHREC)
- The OpenFPGA effort[リンク切れ]
- RC Education Workshop
- Reconfigurable Architectures Workshop
- The George Washington University High Performance Computing Laboratory
- The University of Florida High-Performance Computing & Simulation Research Laboratory
- Reconfigurable computing tools and O/S Support from the University of Wisconsin
- Circuits and Systems Group, Imperial College London
- FHPCA: FPGA High Performance Computing Alliance
- Website of the DRESD (Dynamic Reconfigurability in Embedded System Design) research project
- Advanced topics in computer architecture: chip multiprocessors and polymorphic processors (2003)
- UT Austin TRIPS multiprocessor
- XiRisc/PiCoGA project at University of Bologna, Italy
- COPACOBANA Project, Germany
- BYU Configurable Computing Laboratory's FPGA CAD tool set
- The Morphware Page
- The Configware Page
- ^ Estrin, G. 2002. Reconfigurable computer origins: the UCLA fixed-plus-variable (F+V) structure computer. IEEE Ann. Hist. Comput. 24, 4 (Oct. 2002), 3–9. doi:10.1109/MAHC.2002.1114865
- ^ Estrin, G., "Organization of Computer Systems—The Fixed Plus Variable Structure Computer," Proc. Western Joint Computer Conf., Western Joint Computer Conference, New York, 1960, pp. 33–40.
- ^ C. Bobda: Introduction to Reconfigurable Computing: Architectures; Springer, 2007
- ^ Hauser, John R. and Wawrzynek, John, "Garp: A MIPS Processor with a Reconfigurable Coprocessor," Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97, April 16–18, 1997), pp. 24–33.
- ^ Campi, F.; Toma, M.; Lodi, A.; Cappelli, A.; Canegallo, R.; Guerrieri, R., "A VLIW processor with reconfigurable instruction set for embedded applications," Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International , vol., no., pp.250-491 vol.1, 2003
- ^ Algotronix History
- ^ Hartenstein, R. 2001. A decade of reconfigurable computing: a visionary retrospective. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE 2001) (Munich, Germany). W. Nebel and A. Jerraya, Eds. Design, Automation, and Test in Europe. IEEE Press, Piscataway, NJ, 642–649.
- ^ N. Tredennick: The Case for Reconfigurable Computing; Microprocessor Report, Vol. 10 No. 10, 5 August 1996, pp 25–27.
- ^ A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory
- ^ Generic Address Generator
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