Memory Systems and Pipelined ProcessorsJones & Bartlett Learning, 1996 - 575 ページ The current widespread demand for high performance personal computers and workstations has resulted in a renaissance of computer design. To meet the challenge that this presents to students and professional computer architects, this graduate level text offers an in-depth treatment of the implementation details of memory systems and pipelined processors, the "microarchitecture" of modern computers and microprocessors. The text explores techniques for solving the design problems inherent in computers with high levels of concurrency, such as the demand for a memory system with low latency and high bandwidth, branching, providing precise interrupts, managing dependencies and insuring coherency. Additionally, it examines the difficulties presented by virtual memory in high performance computers. As a thorough compendium of both historical and contemporary implementation techniques, this is an essential sourcebook for computer architecture students and practicing professionals. |
目次
Memory Systems | 1 |
Caches | 15 |
Virtual Memory | 109 |
Memory Addressing and IO Coherency | 201 |
Interleaved Memory and Disk Systems | 231 |
Pipelined Processors | 287 |
Branching | 317 |
Dependencies | 351 |
Exceptions and Interrupts | 425 |
Enhanced Implementations | 467 |
Vector Processors | 507 |
References | 541 |
| 567 | |
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多く使われている語句
address space allocation bandwidth block bytes Cache Address cache design cache miss clock period Computer Architecture condition code Cray Cray X-MP cycle data cache Decode delay discussed in Chapter discussed in Section disk displacement effective address entry example execution unit floating point frame address frame table hardware implementation in-order instruction cache instruction fetch instruction queue integer Intel interleaved memory issue Kbytes latency load main memory multilevel name translation operands operating system out-of-order page fault page table Pentium pipeline pipelined processors Pmiss PowerPC 601 precise interrupts prediction prefetching problem program counter real address reduce register file release reorder buffer reservation table result Sector Name segment set index shown in Figure speedup strategy superpipelined superscalar technique TI ASC tion true dependencies unified cache valid bit vector processors virtual address virtual memory system write back